Campus Event Calendar

Event Entry

What and Who

Circuit Delay Minimization Using Convex Optimization

Stephan-Alexander Ariesanu
Max-Planck-Institut für Informatik - D1
AG1 Mittagsseminar (own work)
AG 1  
AG Audience

Date, Time and Location

Tuesday, 10 September 2019
30 Minutes
E1 4


As circuits grow in complexity the problem of sizing the gates becomes increasingly complex. This Bachelors talk will discuss how convex optimization, in particular geometric programming, can be used in order to find the ideal gate sizes in reasonable time. We will also try to find out how topological changes (which don't change the underlying computation) alter the delay. The underlying delay model is logical effort as described by Ivan Sutherland and Bob Sproull. The talk will present both the current state of the literature and present the challenges which the bachelor thesis will try to overcome.


Christoph Lenzen
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Christoph Lenzen, 09/09/2019 12:52
Christoph Lenzen, 08/12/2019 10:16 -- Created document.