Campus Event Calendar
Event Entry
New for: D3
What and Who
Multiclock Esterel: Towards a unifed language for synchrony and asynchrony
R.K. Shyamasundar
School of Technology & Computer Science Tata Institute of Fundamental Research Mumbai India
Informatik-Kolloquium
AG 1, AG 2, AG 3, AG 4
Expert Audience
Note: We use this to send email in the morning.
Date, Time and Location
Friday, 8 June 2001
15:00
-- Not specified --
45 - FR 6.2
HS 001
Saarbrücken
Abstract
VLSI circuit design has gained considerably from the
introduction of hardware description languages (or HDLs).
While these languages are well suited to describe circuits
in great detail, they are found wanting when attempting
formal verification of circuits. VHDL is the de facto
standard used in the VLSI industry and given the wide
variety of tools that exists to carry out simulations for
circuit specifications in VHDL, it behooves one to explore
the possibility of interfacing it with synchronous
programming languages to handle higher levels of abstraction
in circuit design.
In this talk, we show how the paradigm of multiclock Esterel
provides a framework for the design of multi-clocked systems
and asynchronous systems. We show how Multi-clock Esterel
while preserving the synchrony features embeds Communicating
Reactive Processes (CRP) proposed as a formalism for
integrating synchrony and asynchrony and provides a unified
framework for network of synchronous systems. It can also be
used for modelling distributed timed systems. Further,
Multiclock Esterel can be used for modelling in conjunction
with VHDL to enable formal verification of circuit
behaviour. We shall also show that language captures the
VHDL timing model succinctly.
The language can be used either in conjunction with VHDL or
as a replacement depending on the requirements at hand. When
ed in conjunction, Multiclock Esterel can be used to
describe circuits at higher levels of abstraction while VHDL
can be used to describe the signal propagation
characteristics. On the other hand, it is conceivable that
whole circuits can be described entirely in Multiclock
Esterel Translations of VHDL into Multiclock Esterel could
be used to prove behavioral characteristics of a circuit or
of a component thereof.
introduction of hardware description languages (or HDLs).
While these languages are well suited to describe circuits
in great detail, they are found wanting when attempting
formal verification of circuits. VHDL is the de facto
standard used in the VLSI industry and given the wide
variety of tools that exists to carry out simulations for
circuit specifications in VHDL, it behooves one to explore
the possibility of interfacing it with synchronous
programming languages to handle higher levels of abstraction
in circuit design.
In this talk, we show how the paradigm of multiclock Esterel
provides a framework for the design of multi-clocked systems
and asynchronous systems. We show how Multi-clock Esterel
while preserving the synchrony features embeds Communicating
Reactive Processes (CRP) proposed as a formalism for
integrating synchrony and asynchrony and provides a unified
framework for network of synchronous systems. It can also be
used for modelling distributed timed systems. Further,
Multiclock Esterel can be used for modelling in conjunction
with VHDL to enable formal verification of circuit
behaviour. We shall also show that language captures the
VHDL timing model succinctly.
The language can be used either in conjunction with VHDL or
as a replacement depending on the requirements at hand. When
ed in conjunction, Multiclock Esterel can be used to
describe circuits at higher levels of abstraction while VHDL
can be used to describe the signal propagation
characteristics. On the other hand, it is conceivable that
whole circuits can be described entirely in Multiclock
Esterel Translations of VHDL into Multiclock Esterel could
be used to prove behavioral characteristics of a circuit or
of a component thereof.
Contact
Christian Schulte
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