A Ray Tracing Hardware Architecture for Dynamic Scenes

algorithm, which has a lot of limitations. Especially reflections and
refractions are difficult to approximate. The SaarCOR Ray Tracing
Hardware Architecture solves these problems as it implements the ray
tracing algorithm with all its advantages into a single special purpose
chip.
This talk is about the general SaarCOR architecture and the recently
finished prototype implementation. This prototype implements a ray
tracing pipeline on a single FPGA chip and achieves realtime performance
at a resolution of 512x384 for non trivial scenes. A demonstration of
the prototype will be given.