As circuits grow in complexity the problem of sizing the gates becomes increasingly complex. This Bachelors talk will discuss how convex optimization, in particular geometric programming, can be used in order to find the ideal gate sizes in reasonable time. We will also try to find out how topological changes (which don't change the underlying computation) alter the delay. The underlying delay model is logical effort as described by Ivan Sutherland and Bob Sproull. The talk will present both the current state of the literature and present the challenges which the bachelor thesis will try to overcome.