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Event Entry

What and Who

Fault-tolerant pulse synchronization with stable output frequencies (Master thesis)

Rahul Mudambi Venkatesh
Max-Planck-Institut für Informatik - D1
AG1 Mittagsseminar (own work)
AG 1  
AG Audience

Date, Time and Location

Friday, 2 June 2023
30 Minutes
E1 4


Complex microprocessors are divided into parts that are clocked by different sources. In such a setting, a small clock skew between the parts reduces communication latencies between them. We propose a novel fault-tolerant pulse synchronization algorithm that guarantees a small skew with output frequencies that are at least as stable as the worst reference clock of a non-faulty node and allows recovery of transiently failed nodes. We mainly focus on the hardware implementation details of the proposed algorithm and justify our design choices. Finally, we present and discuss some selected simulations for the proposed digital circuit and demonstrate the synchronization guarantees of the algorithm.


Roohani Sharma
+49 681 9325 1116
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Virtual Meeting Details

527 278 8807
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Tags, Category, Keywords and additional notes

If you wish to attend the talk online, but do not have the zoom password, contact Roohani Sharma at

Roohani Sharma, 06/01/2023 13:29
Roohani Sharma, 05/23/2023 14:45 -- Created document.