We present an axiomatic framework, implemented in Coq, to define weak memory
models w.r.t. several parameters: local reorderings of reads and writes, and
visibility of inter and intra processor communications through memory,
including full store atomicity relaxation. Thereby, we give a formal hierarchy
of weak memory models, in which we provide a formal study of what should be the
action and placement of fences to restore a given model such as Sequential
Consistency from a weaker one. Finally, we provide a tool, diy, that tests a
given machine to determine the architecture it exhibits. We detail the results
of our experiments on Power and the model we extract from it. This identified
an implementation error in Power 5 memory barriers (for which IBM is providing
a software workaround); our results also suggest that Power 6 does not suffer
from this problem.