Campus Event Calendar
Event Entry
What and Who
Generating Code from Abstract VHDL Models
Mohamed AbdelMaksoud
International Max Planck Research School for Computer Science - IMPRS
PhD Application Talk
AG 1, AG 3, AG 4, AG 5, SWS, RG1, MMCI
Public Audience
English
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Date, Time and Location
Monday, 19 October 2009
09:00
240 Minutes
E1 4
024
Saarbrücken
Abstract
Safety-critical hard real time systems as the flight control computer in avionics or airbag control software in the automotive industry need to be validated for their correct behavior. Besides the functional correctness, timely task completion is essential, i.e. the worst-case execution time (WCET) of each task in the system has to be determined. Saarland University and AbsInt GmbH have successfully developed the aiT WCET analyzer for computing safe upper bounds on the WCET of a task. The computation is mainly based on abstract interpretation of timing models of the processor and its periphery. Such timing models are currently hand-crafted by human experts. Therefore their implementation is a time-consuming and error-prone process. This thesis presents an abstraction-aware compiler for automatically generating efficient pipeline analyzes out of abstracted timing models that could be derived from formal VHDL specifications.
Contact
imprs
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Jennifer Gerling, 10/07/2009 15:36 -- Created document.