Precise Interrupts in Processors with Out-of-Order Execution

level parallelism. Several instructions can be executed in the functional
units in a single machine cycle. Since the functional units have different
latencies, instructions can complete out-of-order, and therefore it is no
longer guaranteed that the status of the processor is updated in sequential
program order.
Up-to-date microprocessors provide fast I/O, virtual memory and support the
full IEEE-754 floating point standard. All that calls for a powerful mechanism
for the support of precise nested interrupts. The design of such a mechanism
is one of the main design challenges in a processor. It becomes even more
complex in processors with out-of-order execution. In order to make the
interrupts precise, the processor must be recovered from the out-of-order
state to the in-order state. In commercial microprocessors, the problem of
combining precise interrupts and out-of-order execution has been solved
in 1995 for the first time.
In the classic work of Smith and Pleszkun, several interrupt mechanisms for
the solution of this problem are proposed: the reorder buffer, the
future file, and the history buffer.
We have integrated these mechanisms in a RISC processor with out-of-order
execution and have proven their correctness.
The three design variants have been compared based on the hardware cost,
the cycle time, and the average number of cycles per instruction (CPI).
In this talk, we present the result of our analysis.