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What and Who
Title:Predictable Execution of Real-Time Applications on Many-Core Platforms
Speaker:Matthias Becker
coming from:KTH Royal Institute of Technology
Speakers Bio:Matthias Becker is a postdoc researcher at KTH Royal Institute of Technology since February 2018. He received his B.Eng. degree in Mechatronics/Automation Systems from the University of Applied Sciences Esslingen, Germany in 2011. In the year 2013 he got his M.Sc. degree in Computer Science specializing in embedded computing from the University of Applied Sciences Munich, Germany. He received his Licentiate and PhD degree in Computer Science and Engineering from Mälardalen University, Sweden in 2015 and 2017 respectively. Matthias has been a visiting researcher at CISTER - Research Centre in Real-Time and Embedded Computing Systems in Porto, Portugal for two months in 2015 and for three months in 2016.
Event Type:SWS Colloquium
Visibility:D1, D2, D3, INET, D4, D5, SWS, RG1, MMCI
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Level:AG Audience
Language:English
Date, Time and Location
Date:Friday, 8 March 2019
Time:10:30
Duration:60 Minutes
Location:Kaiserslautern
Building:G26
Room:111
Abstract
Nowadays, innovation in many industrial areas is software driven, where existing software functions become more complex and new software functions are constantly introduced. The rapid increase in functionality comes along with a steep increase in software complexity. To cope with this transition, current trends shift away from today’s distributed architectures towards integrated architectures. Here, previously distributed functionality is consolidated on fewer, more powerful, computers. Such a trend can for example be observed in the automotive or avionics domain. This can ease the integration process, reduce the hardware complexity, and ultimately save costs.

One promising hardware platform for these powerful embedded computers is the many-core processor. A many-core processor hosts a vast number of compute cores, that are partitioned on clusters which are connected by a Network-on-Chip. However, ensuring that real-time requirements are satisfied in the presence of contention in shared resources, such as memories, remains an open issue. In addition, industrial applications are often subject to timing constraints on the data propagation through a chain of semantically related tasks. Such requirements pose challenges to the system designer as they are only able to verify them after the system synthesis (i.e. very late in the design process).
In this talk, we present methods that transform timing constraints on the data propagation delay into precedence constraints between individual task instances. An execution framework for the cluster of the many-core is proposed that allows access to cluster external memory while it avoids contention on shared resources by design. Spatial and temporal isolation between different clusters is provided by a partitioning and configuration of the Network-on-Chip that further reduces the worst-case access times to external memory.

Contact
Name(s):Mouna Litz
Video Broadcast
Video Broadcast:YesTo Location:Saarbrücken
To Building:E1 5To Room:029
Meeting ID:
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Created:
Mouna Litz/MPI-SWS, 02/26/2019 02:40 PM
Last modified:
Uwe Brahm/MPII/DE, 03/08/2019 07:01 AM
  • Mouna Litz, 02/27/2019 03:50 PM
  • Mouna Litz, 02/26/2019 02:47 PM -- Created document.