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What and Who
Title:Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures
Speaker:Marvin Damschen
coming from:Karlsruhe Institute of Technology
Speakers Bio:Marvin Damschen received his Ph.D. (Dr.-Ing.) in Computer Science from the Karlsruhe Institute of Technology (KIT), Germany, under the supervision of Prof. Dr. Jörg Henkel in Dec. 2018. Currently, he is a postdoctoral researcher at the Chair for Embedded Systems at KIT. His main research interests are timing analysis and architectures for real-time embedded systems with special focus on runtime-reconfigurable architectures.
Marvin Damschen received a B.Sc. degree - with distinction - and M.Sc. degree - with distinction - in Computer Science with a minor in Mathematics from the University of Paderborn, Germany, in 2012 and 2014, respectively.
Event Type:SWS Colloquium
Visibility:D1, D2, D3, INET, D4, D5, SWS, RG1, MMCI
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Level:AG Audience
Language:English
Date, Time and Location
Date:Thursday, 4 April 2019
Time:14:00
Duration:60 Minutes
Location:Kaiserslautern
Building:G26
Room:111
Abstract
Real-time embedded systems need to be analyzable for execution time guarantees. Despite significant scientific advances, however, timing analysis lags years behind current microarchitectures with out-of-order scheduling pipelines, several hardware threads and multiple (shared)cache layers. To satisfy the increasing demand for predictable performance, analyzable performance features are required. We introduce runtime-reconfigurable instruction set processors as one way to escape the scarcity of analyzable performance features while preserving the flexibility of the system. To this end, we first present a reconfiguration controller for guaranteed reconfiguration delays of accelerators onto an FPGA. We propose a novel timing analysis approach to obtain worst-case execution time (WCET) guarantees for applications that utilize runtime-reconfigurable custom instructions (CIs), which
each utilize one or more accelerators. Given the constrained reconfigurable area of an FPGA, we solve the problem of selecting CIs for each computational kernel of an application to optimize its worst-case execution time. Finally, we show that runtime reconfiguration provides the unique feature of optimized static WCET guarantees and optimization of the average-case execution time (maintaining statically-given WCET guarantees) by repurposing reconfigurable area for different selections of CIs at runtime.
Contact
Name(s):Mouna Litz
Video Broadcast
Video Broadcast:YesTo Location:Saarbrücken
To Building:E1 5To Room:029
Meeting ID:SWS Space 2 (6312)
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Created:
Mouna Litz/MPI-SWS, 03/21/2019 11:05 AM
Last modified:
Uwe Brahm/MPII/DE, 04/04/2019 07:01 AM
  • Carina Schmitt, 03/26/2019 04:37 PM
  • Mouna Litz, 03/21/2019 11:23 AM
  • Mouna Litz, 03/21/2019 11:22 AM -- Created document.