Campus Event Calendar
Event Entry
What and Who
The evolution of the synchronous programming model
Gerard Berry
Esterel Technologies
SWS Distinguished Lecture Series - Winter
Gérard Berry is the father of the Esterel language. Before joining Esterel Technologies in January 2001, Mr. Berry was the Director of Research at Ecole des Mines de Paris (EMP), Director of the Applied Mathematics Center (CMA) of EMP, and co-head of the joint EMP/INRIA Meije project (INRIA is the largest European research center in computer science and automation).
His research activities include mathematical logic, programming language design, semantics, and implementation, reactive and real-time programming, synchronous circuit design and synthesis, and automatic verification of finite-state systems. His teaching activities include the theory of automata and its relation to Boolean algebra, computability theory, the lambda calculus, electronic circuit design and verification, and reactive and real-time programming.
Mr. Berry is a member of Académie des sciences, Académie des technologies, and Academia Europaea. He received the Grand Prix of the EADS foundation in 2005, the French Science and Defense award in 1999, the Monpetit Price of the French Académie des sciences in 1989, and the Bronze Medal of CNRS in 1979. He has given 36 invited talks in international conferences, mostly on Esterel, and written more than 30 reference papers for conferences, journals, and books.
During his research and teaching activities, Mr. Berry worked closely with Dassault Aviation, which has strongly supported the development of the Esterel language and has regularly funded his research through R&D contracts in the last 12 years. He also worked with Cadence on hardware/software co-design and entry languages, with Intel to explore the possible use of Esterel in aggressive microprocessor design and synthesis, and with Synopsys on hardware synthesis from Esterel. All these works were funded by research grants given to him by the corresponding companies.
AG 1, AG 2, AG 3, AG 4, AG 5, SWS, RG1, RG2
Expert Audience
English
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Date, Time and Location
Wednesday, 29 October 2008
16:00
60 Minutes
E1 5
204
Saarbrücken
Abstract
The synchronous programming model has become a major model in industrial embedded systems design (avionics, railways, SoCs, etc.) because it reconciles concurrency and determinism. For hardware systems, synchrony naturally fits the RTL paradigm and makes it fully rigorous. For software systems,synchrony naturally fits with two classical engineering models informally based on cyclic computations: data-flow block diagrams and control-flow state machines. The initial synchronous languages were dedicated either to data-flow designs (Lustre, Signal, etc.) or to control-oriented designs (Esterel, SyncCharts, etc.). The more recent languages completely unify both point of views: Esterel v7 keeps all the temporal primitives of the initial Esterel language and adds poweful datapath definition mechanisms, while Scade 6 provides its user with an graphical merge of data-flow diagrams and hierarchical state machines. We present the principles of these recent unifications, which are non-trivial: while it is quit easy to merge the drawing styles, it is much harder to do so by respecting the semantic properties of the languages. We show how the new languages simplify application design, and how they also provide formal verification systems with vital static information. We finally discuss new proposals to extend the original synchronous model into mixed synchronous / asynchronous that try to keep non-determinism under control.
Contact
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Video Broadcast
Yes
Saarbrücken
E1 5
019
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Brigitta Hansen, 09/24/2008 15:37 -- Created document.