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Event Entry

New for: D1, D2

What and Who

Fast Priority Queues for Cached Memory

Peter Sanders
Max-Planck-Institut für Informatik - AG 1
AG1 Mittagsseminar (own work)
AG 1, AG 2  
AG Audience
-- Not specified --

Date, Time and Location

Wednesday, 16 December 98
13:30
-- Not specified --
46
024
Saarbrücken

Abstract

The cache hierarchy prevalent in todays high performance processors

has to be taken into account in order to design algorithms which
perform well in practice. We advocates the approach to adapt external
memory algorithms to this purpose. We exemplify this approach and the
practical issues involved by engineering a fast priority queue suited
to external memory and cached memory which is based on k-way merging.
It improves previous external memory algorithms by constant factors
crucial for transferring it to cached memory. Running in the cache
hierarchy of a workstation the algorithm is around three times faster
than an optimized binary heap implementation.

Contact

Peter Sanders
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