Hardware/Software Interaction in Embedded MPSoC Systems

embedded systems are applied. This results from a trend to implement more
and more complex functionality or to integrate functionality that was
originally spread over many tiny controllers into one chip. On the other
hand many of those systems are battery powered or have to have a small form
factor and cannot be intensively cooled. Thus, they are heavily constraint
with respect to their power consumption. This favors the utilization of
multiprocessor systems-on-chip (MPSoCs) over higher clocked single-cores.
Since cost per piece is tremendously important in embedded design efficient
implementation and utilization of the available hardware resources are
imperative.
Therefore, this talk will introduce a technique to model hardware/software
dependencies of embedded MPSoCs relevant for code generation and system
layout in the context of model-based design.
An additional challenge arises if MPSoCs are applied in application domains
that have to adhere to safety and hard real-time constraints.
State-of-the-art MPSoCs do not lend themselves well to the kind of analysis
necessary to get their application certified by the according authorities.
Therefore a novel shared-memory bus arbitration scheme is presented that
enables tight bounds on worst-case execution times while maintaining high
bus utilization.