On the Design of IEEE Compliant Floating-Point Units and Their Quantitative Analysis

for the design of an IEEE compliant floating-point unit (FPU).
All the FPU architectures considered in this work are fully compliant
with the IEEE standard, support both double and single precision
numbers, and support denormal and special values in hardware.
The following design options are considered: (a) the internal
representation of floating-point numbers; (b) the rounding algorithms;
(c) sharing of a rounding unit or dedicated rounding units for each
functional unit; (d) implementation of the floating-point multiplier;
and (e) implementation of the floating-point divider.

A quantitative analysis demonstrates that the choice of the rounding
architecture has a larger impact on the performance than the choice of
the FP multiplication or the FP division implementation. The impact
of the rounding architecture choice on the cost is only small. The rounding
architecture that uses dedicated rounding units provides the best
performance with only small additional cost, so that this rounding architecture
seems to be the best choice in floating-point implementations.