Campus Event Calendar
Event Entry
What and Who
Precise Interrupts in Processors with Out-of-Order Execution
Holger Leister
Seminar des Graduiertenkollegs
AG 1, AG 2
AG Audience
English
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Date, Time and Location
Monday, 9 February 98
16:00
60 Minutes
Geb. 45
015
Saarbrücken
Abstract
Current microprocessors achieve high performance by exploiting instruction level parallelism. Several instructions can be executed in the functional units in a single machine cycle. Since the funtional units have different latencies, instructions can complete out-of-order and therefore it is no longer guaranteed that the status of the processor is updated in sequential program order.
Up-to-date microprocessors provide fast I/O, virtual memory and support the full IEEE floating point standard. All that calls for a powerful interrupt mechanism. The design of such a mechanism is one of the main design challenges in a processor. This task becomes even more complex in processors with out-of-order execution. In order to make the interrupts precise, the processor must have a recovery mechanism which reestablishes the in-order state. In commercial microprocessors, the problem of combining precise interrupts and out-of-order execution was first solved in 1995. In this talk, we present several mechanisms for the solution of this problem: the reorder buffer, the future file and the history buffer.
Contact
Ülkü Coruh
9325-526
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