Max-Planck-Institut für Informatik
max planck institut
informatik
mpii logo Minerva of the Max Planck Society
 

MPI-INF or MPI-SWS or Local Campus Event Calendar

New for: D1, D2, D3, D4, D5
<< Previous Entry Next Entry >> New Event Entry Edit this Entry Login to DB (to update, delete)
What and Who
Title:Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems
Speaker:Geoffrey Nelissen
coming from:CISTER, Porto
Speakers Bio:Geoffrey Nelissen was born in Brussels, Belgium in 1985. He earned his M.Sc. degree in Electrical Engineering at Université Libre de Bruxelles (ULB), Belgium in 2008. He then worked during four years as a Ph.D. student in the PARTS research unit of ULB. In 2012, he received his Ph.D. degree under the supervision of Professors Joël Goossens and Dragomir Milojevic, on the topic "Efficient Optimal Multiprocessor Scheduling Algorithms for Real-Time Systems". He is currently working at CISTER, Porto, Portugal, as an associate researcher in the area of real-time scheduling, embedded, distributed and safety critical system design and analysis.
Event Type:SWS Colloquium
Visibility:D1, D2, D3, D4, D5, SWS, RG1, MMCI
We use this to send out email in the morning.
Level:AG Audience
Language:English
Date, Time and Location
Date:Wednesday, 10 August 2016
Time:10:30
Duration:90 Minutes
Location:Kaiserslautern
Building:G26
Room:111
Abstract
The existing gap between the processor and main memory operating speeds motivated the introduction of intermediate cache memories to accelerate the average access time to instructions and data accessed by programs running on the processor. The introduction of cache memories in modern computing platforms is the cause of important variations in the execution time of each task, depending on whether the instruction and data it requires are already loaded in the cache or not. Many works have focused on analyzing the impact of preemptions on the worst-case execution time (WCET) and worst-case response time (WCRT) of tasks in preemptive systems. Indeed, the preempted tasks may suffer additional cache misses if its memory blocks are evicted from the cache during the execution of preempting tasks. These evictions cause extra accesses to the main memory, which result in additional delays in the task execution. This extra cost is usually referred to as cache-related preemption delays (CRPDs).

Several approaches use information about the tasks' memory access patterns to bound and incorporate preemption costs into the WCRT analysis. These approaches all result in pessimistic WCRT bounds due to the fact that they do not consider the variation in memory demand for successive instances of a same task. They usually assume that the useful cache content for the task is completely erased between two of its executions. However, in actual systems, successive instances of a task may re-use most of the data and instructions that were already loaded in the cache during previous executions.
During this talk, we will discuss the concept of persistent cache blocks from a task WCRT perspective, and will present how it can be used to reduce the pessimism of the WCRT analysis for fixed priority preemptive systems. Then, we will introduce techniques exploiting this notion of cache persistence to pre-configure systems so as to improve their runtime behavior.
Contact
Name(s):Vera Schreiber
Video Broadcast
Video Broadcast:YesTo Location:Saarbrücken
To Building:E1 5To Room:029
Tags, Category, Keywords and additional notes
Note:
Attachments, File(s):
Created by:Vera Schreiber/MPI-SWS, 08/02/2016 01:58 PMLast modified by:Uwe Brahm/MPII/DE, 11/24/2016 04:13 PM
  • Christian Klein, 10/13/2016 03:47 PM
  • Vera Schreiber, 08/02/2016 02:03 PM -- Created document.