Using Total Informedness for Partial Design Verification

to have a non-elementary computational complexity for cases with multiple
levels of information among the components to be synthesized. This is also
true for cases in which the implementations of some components has been
fixed. The high complexity makes the usability of this methods
questionable except for cases in which the information hierarchy is flat.
However, there have been no algorithms for checking this so far.

We present a novel construction that allows the analysis of the
information flow through a set of given automata. It detects architectures
that distribute information globally but possibly delayed. A simple
example shows how synthesis can be performed in these cases in practice.