Campus Event Calendar
Event Entry
What and Who
Modeling and Testing of Multi-cycle Power Droop Faults
Santanu Bhowmick
Indian Statistical Institute – India
PhD Application Talk
AG 1, AG 2, AG 3, AG 4, AG 5, SWS, RG1, MMCI
Public Audience
English
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Date, Time and Location
Monday, 7 May 2012
11:00
60 Minutes
E1 4
024
Saarbrücken
Abstract
A significant voltage droop may occur at a power supply via when multiple gates in its feed region undergo simultaneous logic transitions. This may cause timing faults and may invalidate a stuck-at fault test. Further, inductance of power grid lines can prolong and accentuate this effect over more than one clock cycle.
We propose a model for these multi-cycle droop faults (MDF) and describe an efficient SAT-based test-pattern generation method for such faults in combinational and full-scan circuits. Experimental results on ISCAS85, ISCAS89 and ITC99 benchmark circuits have been reported to demonstrate the efficacy of the method.
Contact
IMPRS Office Team
9325 1800
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Marc Schmitt, 05/04/2012 13:41 -- Created document.