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What and Who
Title:Circuit Delay Minimization Using Convex Optimization
Speaker:Stephan-Alexander Ariesanu
coming from:Max-Planck-Institut für Informatik - D1
Speakers Bio:
Event Type:AG1 Mittagsseminar (own work)
Visibility:D1
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Level:AG Audience
Language:English
Date, Time and Location
Date:Tuesday, 10 September 2019
Time:13:00
Duration:30 Minutes
Location:Saarbrücken
Building:E1 4
Room:024
Abstract
As circuits grow in complexity the problem of sizing the gates becomes increasingly complex. This Bachelors talk will discuss how convex optimization, in particular geometric programming, can be used in order to find the ideal gate sizes in reasonable time. We will also try to find out how topological changes (which don't change the underlying computation) alter the delay. The underlying delay model is logical effort as described by Ivan Sutherland and Bob Sproull. The talk will present both the current state of the literature and present the challenges which the bachelor thesis will try to overcome.
Contact
Name(s):Christoph Lenzen
Video Broadcast
Video Broadcast:NoTo Location:
Tags, Category, Keywords and additional notes
Note:
Attachments, File(s):
  • Christoph Lenzen, 09/09/2019 12:52 PM
  • Christoph Lenzen, 08/12/2019 10:16 AM -- Created document.