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New for: D1, D3, D4, D5

What and Who

Algorithms for Parallel Cache Hierarchies

Guy Blelloch
Carnegie Mellon University
SWS Colloquium

Guy Blelloch is a Professor of Computer Science at Carnegie Mellon.
His research interests are in programming languages and algorithms and how they interact
with an emphasis on parallel computation.   Blelloch designed and implemented the parallel
programming language NESL, a language designed for easily expressing and analyzing parallel
algorithms and has worked on issues in scheduling, algorithm design,
cache efficiency, garbage collection, and synchronization primitives.
AG 1, AG 3, AG 4, AG 5, SWS, RG1, MMCI  
AG Audience
English

Date, Time and Location

Friday, 5 March 2010
15:00
60 Minutes
E1 5
5th floor
Saarbrücken

Abstract


Cache hierarchies in multicore computers are quite complex consisting of many levels
of both shared and private caches.  Designing algorithms and applications for such caches
can be very complicated although often necessary to get good performance.
We discuss approaches of capturing the locality of a parallel algorithm at a high-level
requiring little work by the algorithm designer or programmer and then using this
along with an appropriate thread scheduler to get good cache performance on a variety
of parallel cache configurations.   I will describe results for private caches,
shared caches and some new results on multiple level cache hierarchies.
In all cases the same algorithms can be used, but the scheduler needs to be changed.
The approach makes use of ideas on cache oblivious algorithms.

Contact

Bettina Bennett
0631-9303-9602
--email hidden

Video Broadcast

Yes
Saarbrücken
E1 4
24
passcode not visible
logged in users only

Rose Hoberman, 05/07/2010 14:42
Bettina Peden-Bennett, 03/04/2010 15:39 -- Created document.