Complex microprocessors are divided into parts that are clocked by different sources. In such a setting, a small clock skew between the parts reduces communication latencies between them. We propose a novel fault-tolerant pulse synchronization algorithm that guarantees a small skew with output frequencies that are at least as stable as the worst reference clock of a non-faulty node and allows recovery of transiently failed nodes. We mainly focus on the hardware implementation details of the proposed algorithm and justify our design choices. Finally, we present and discuss some selected simulations for the proposed digital circuit and demonstrate the synchronization guarantees of the algorithm.