Metastability-Containing Sorting Networks

Metastability-Containing sorting networks serve as a central building block in fault-tolerant clock-synchronization algorithms on chip.

In this paper we designed and analyzed, both theoretically and via simulations, a metadtability-containing sorting network.

Informally, a metastable-containing combinational circuit is a circuit that can handle metastable inputs and still produces meaningful outputs.

My thesis deals with the implementation of the circuit, testing it and
comparing it with similar circuits.
I clarify how requiring metastability containment affects the design process of a microchip.
As we go along we find a way to transform a "theoretical" circuit to a netlist of real hardware cells.