Campus Event Calendar

Event Entry

What and Who

Design of a Pipelined Packet-Forwarding Floating Point Processor.

David W. Matula
Professor of Computer Science and Engineering, SMU, Dallas TX, USA
AG 1, AG 2, AG 3, INET, AG 4, AG 5, D6, RG1, SWS  
AG Audience

Date, Time and Location

Friday, 17 January 97
60 Minutes
45 - FB14


Microprocessors designed to operate at 300-500 MHz typically have
their floating point multiply and add unit execution phases deeply
pipelined, with less than 15 logic levels per cycle. Dependent floating
point operations severly impact the efficiency of such pipelines.\\
This presentation describes a research project at SMU focusing on a new
paradigm for floating point data forwarding in such pipelines. The foundations
of our proposed Packet-Forwarding format are presented. This format
allows the sign,exponent and principal part of a floating point result to
be forwarded between cooperating pipelines before rounding. The format for
forwarding can be redundant (e.g. borrow-save) and the result is completed
by the output of a carry round packet which is forwarded one cycle later
as determined by special rounding circuity. The rounder also outputs the
conventional IEEE 754 formated result for retirement to a register after one

more cycle of delay, a feature which does not add to the latency for the
forwarded output.\\, a feature which does not add to the latency for the
We present a high level architecture for the rounder. Also presented are
multiplier and adder pipes accepting the temporally staggered packet forwarding
input. Compared to a 4 execution-cycle conventional forwarding floating point
design our unit cuts the latency in half and reduces the stall cycles by a
factor of three in processing data dependent operations. The speedup occurs
with preservation of IEEE754 binary floating point compatibility.


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