Campus Event Calendar

Event Entry

What and Who

Hazard-Free Clock Synchronization (PhD defense)

Johannes Bund
Max-Planck-Institut für Informatik - D1
AG1 Mittagsseminar (own work)
AG 1, INET, AG 5, RG1, SWS, AG 2, AG 4, D6, AG 3  
MPI Audience

Date, Time and Location

Tuesday, 28 February 2023
90 Minutes
Virtual talk
Virtual talk


The growing complexity of microprocessors makes it infeasible to distribute a single clock source over the whole processor with small clock skew. Hence, chips are split into multiple clock regions, which are each covered by a single clock source. This poses a problem for communication between these clock regions. Clock synchronization algorithms promise an advantage over state-of-the-art solutions, such as GALS systems. When clock regions are synchronous the communication latency improves significantly over handshake-based solutions. We focus on implementation of clock synchronization algorithms.

A major obstacle when implementing circuits on clock domain crossings are hazardous signals. Extending the Boolean logic by a third value 'u' we can formally define hazards. In this thesis we describe a theory for design
and analysis of hazard-free circuits. We develop strategies for hazard-free encoding and construction of hazard-free circuits from finite state machines. Furthermore, we discuss clock synchronization algorithms and a possible combination of them.


Johannes Bund
--email hidden

Video Broadcast

E1 4
SWS Space 1 - PIN (6311)

Virtual Meeting Details

939 3073 6219
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logged in users only

Johannes Bund, 02/06/2023 10:53
Johannes Bund, 01/26/2023 15:31
Johannes Bund, 01/26/2023 15:29 -- Created document.