Complex microprocessors are divided into parts that are clocked by different sources. In such a setting, a small clock skew between the parts reduces communication latencies between them. Modeling the distinct clock regions as nodes, the Lynch-Welch pulse synchronization algorithm is a fault-tolerant algorithm that helps achieve a bounded clock skew between them. However, measurement errors of the phase offsets between the clocks result in the deterioration of the stability of the output pulse frequency. Hence, we propose a novel pulse synchronization algorithm where the output frequency is at least as stable as the worst reference clock of a non-faulty node. Further, we allow for nodes that recover from transient faults to resynchronize. Finally, we focus on the implementation and the simulation of the algorithm on hardware.