Campus Event Calendar

Event Entry

What and Who

Fault-tolerant pulse synchronization with stable output frequencie (Master thesis)

Rahul Mudambi Venkatesh
Max-Planck-Institut für Informatik - D1
AG1 Mittagsseminar (own work)
AG 1  
AG Audience

Date, Time and Location

Tuesday, 7 March 2023
30 Minutes
E1 4


Complex microprocessors are divided into parts that are clocked by different sources. In such a setting, a small clock skew between the parts reduces communication latencies between them. Modeling the distinct clock regions as nodes, the Lynch-Welch pulse synchronization algorithm is a fault-tolerant algorithm that helps achieve a bounded clock skew between them. However, measurement errors of the phase offsets between the clocks result in the deterioration of the stability of the output pulse frequency. Hence, we propose a novel pulse synchronization algorithm where the output frequency is at least as stable as the worst reference clock of a non-faulty node. Further, we allow for nodes that recover from transient faults to resynchronize. Finally, we focus on the implementation and the simulation of the algorithm on hardware.


Roohani Sharma
+49 681 9325 1116
--email hidden

Virtual Meeting Details

527 278 8807
passcode not visible
logged in users only

Tags, Category, Keywords and additional notes

If you wish to attend the talk online but do not have the password, contact Roohani Sharma at

Roohani Sharma, 02/27/2023 13:03
Roohani Sharma, 02/02/2023 12:58 -- Created document.