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What and Who

PALS: Plesiochronous and Locally Synchronous Systems

Johannes Bund
Max-Planck-Institut für Informatik - D1
AG1 Mittagsseminar (own work)
AG 1, AG 3, AG 4, RG1, MMCI, AG 2, INET, AG 5, SWS  
AG Audience

Date, Time and Location

Tuesday, 21 July 2020
30 Minutes


Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: (i) by deriving it from a single, central clock source, (ii) by local, free-running oscillators, or (iii) by handshaking between neighboring modules.

Conceptually, each of these solutions is the result of a perceived dichotomy in which (sub)systems are either clocked or fully asynchronous, suggesting that the designer’s choice is limited to deciding where to draw the line between synchronous and asynchronous design.
In contrast, we take the view that the better question to ask is how synchronous the system can and should be. Based on a distributed clock synchronization algorithm, we present a novel design providing modules with local clocks whose frequency bounds are almost as good as those of corresponding free-running oscillators, yet neighboring modules are guaranteed to have a phase offset substantially smaller than one clock cycle. Concretely, parameters obtained from a 15nm ASIC implementation running at 2 GHz yield mathematical worst-case bounds of 30 ps on phase offset for a 32 × 32 node grid network.


Johannes Bund
+49 681 9325 0
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For people outside D1 interested in listening to this talk, please contact Johannes Bund for Zoom login credentials.

Johannes Bund, 07/20/2020 08:20 PM
Johannes Bund, 07/02/2020 08:29 AM
Johannes Bund, 07/02/2020 08:29 AM -- Created document.