abstract: In this talk, I will present a promising approach to leveraging techniques typically associated with theoretical computer science for the design of fault-tolerant hardware. I will discuss how to adapt and extend approaches to fault-tolerance known from the area of distributed computing to this setting. Moreover, I will introduce a novel framework that facilitates seamless integration of individual components (and corresponding formal statements) into larger circuits. Our framework is designed to bridge scales: ultimately, it enables to prove correctness, robustness, and efficiency of fully-flegded systems from bottom to top, starting at the gate level.