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What and Who
Title:Impact of Multicore on Cyber-Physical Systems: challenges andsolutions
Speaker:Dr. Marco Caccamo
coming from:University of Illinois
Speakers Bio:Caccamo received his Ph.D. in computer engineering from Scuola
Superiore Sant’Anna, Pisa, Italy in January 2002 and joined University
of Illinois at Urbana-Champaign shortly after graduation, where he is
a professor of computer science. He also has a courtesy appointment in
the Department of Electrical and Computer Engineering (ECE) at the
University of Illinois. In broad terms, his research interests are
centered on the area of embedded systems. He has worked in close
collaboration with avionics, farming, and automotive industries
developing innovative software architectures and toolkits for the
design automation of embedded digital controllers, and low-level
resource management solutions for real-time operating systems running
on multicore architectures. He has authored/coauthored more than 90
refereed publications in real-time and embedded networked computing
systems. He has been a guest editor of the Journal of Real-Time
Systems and he is the program chair of RTSS'15. He was previously
program chair of RTAS and also served as both general chair of RTAS
and Cyber Physical Systems Week (CPSWeek’11). He was also awarded an
NSF CAREER Award in 2003 and is a senior member of IEEE.
Event Type:SWS Distinguished Lecture Series
Visibility:D1, D2, D3, D4, D5, SWS, RG1, MMCI
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Level:Expert Audience
Language:English
Date, Time and Location
Date:Thursday, 26 November 2015
Time:10:30
Duration:60 Minutes
Location:Saarbrücken
Building:E1 5
Room:002
Abstract
The benefits of adopting emerging multicore processors include
reductions in space, weight, power, and cooling, while increasing CPU
bandwidth per processor. However, the existing real-time software
engineering process is based on the constant worst case execution time
(WCET) assumption, which states that the measured worst case execution
time of a software task when executed alone is the same as when that
task is running together with other tasks. While this assumption is
correct for single-core chips, it is NOT true for multicore chips. As
it is now, the interference between cores can cause delay spikes as
high as 600% in industry benchmarks. This presentation reviews main
challenges faced by the embedded industry today when adopting
multicore in safety critical embedded systems. A discussion on the
notion of Single Core Equivalence follows.
Contact
Name(s):Vera Schreiber
Video Broadcast
Video Broadcast:YesTo Location:Kaiserslautern
To Building:G26To Room:111
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Created by:Vera Schreiber/MPI-SWS, 11/17/2015 10:09 AMLast modified by:Uwe Brahm/MPII/DE, 11/24/2016 04:14 PM
  • Vera Schreiber, 11/17/2015 02:17 PM
  • Vera Schreiber, 11/17/2015 10:16 AM -- Created document.