Ian has a PhD in Electrical Engineering from Imperial College, London. He was introduced to asynchronous circuit and systems design while working with Sutherland, Sproull and Associates, Inc. At Apple Computer he helped develop a software-programmable gate array chip prototype -- one of his few clocked chip designs.
He joined Sun Labs in 1992, which became Oracle Labs in 2010, where his research focused on high speed asynchronous circuits, clock domain crossing circuits, and using Formal Methods to detect bugs in large hardware designs. Ian has worked closely with chip designers in product divisions, applying asynchronous circuit design techniques to greatly improve both the performance and the reliability of their products.

AG 1   Info

AG Audience

English

30 Minutes

Saarbrücken

Large chips designs commonly contain multiple clock domains with many
clock-domain crossings, multi-cycle paths, and embedded circuits for test. Long combinational logic delays introduce vulnerabilities for glitch-related failures. Unfortunately, such glitches can be introduced by logic synthesis and logic optimization tools. This is because the synthesis and optimization algorithms do not take into account the fact that signals from other timing domains can change at arbitrary times. Simulation-based techniques can miss these glitches because of the large number of values and timing scenarios. Furthermore, none of the commercially available tools that we have tried provide a comprehensive solution. To detect these unintentional glitches paths, we have implemented a tool that applies Formal Methods to exhaustively explore RTL circuits. We have applied our approach to large modules from real, commercial microprocessor designs and have found real glitches.

Sándor Kisfaludi-Bak

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